Method for fabricating trench type transistor

ABSTRACT

An epitaxial layer is formed on the semiconductor substrate. A nitride doping region is then formed at a surface of the epitaxial layer. A hard mask layer is formed on the epitaxial layer. The hard mask layer comprises at least an opening. Through the opening, agate trench is etched into the epitaxial layer. A gate is formed within the gate trench. The hard mask layer is removed such that the gate protrudes from the surface of the epitaxial layer. An ion well is formed within the epitaxial layer. A source doping region is formed within the ion well. An upper portion of the gate that protrudes from the surface of the epitaxial layer is selectively oxidized to thereby form an oxide capping layer. Using the oxide capping layer as an etching hard mask, the epitaxial layer is self-aligned etched to thereby form a contact hole.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.13/740,250 filed Jan. 13, 2013, which is included in its entirety hereinby reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductortechnology. More particularly, the present invention relates to a methodfor fabricating a trench type transistor.

2. Description of the Prior Art

As known in the art, the rise of on-resistance of traditional planarpower DMOS devices (DMOS) is contributed from the channel region, theaccumulation layer and junction field effect transistor (JFET).

In order to reduce the resistance of the above-mentioned area, trenchtype power devices (UMOS) are proposed. Since JFET region does not existin a UMOS, the cell size can be reduced and the channel density isincreased, thereby resulting in a lower on-resistance. However, as thecell size shrinks, the gap or space between the gate and the contactwindow also reduces, leading to overly issues.

SUMMARY OF THE INVENTION

It is therefore one object of the present invention to provide animproved trench type power semiconductor device and fabrication methodthereof in order to solve the above-mentioned overlay problems.

According to an embodiment, a method for fabricating a trench typetransistor device is disclosed. A semiconductor substrate is provided.An epitaxial layer is grown on the semiconductor substrate. A hard masklayer is formed on the epitaxial layer. The hard mask layer comprises atleast an opening. Through the opening, agate trench is etched into theepitaxial layer. Agate oxide layer is then formed in the gate trench. Agate is formed within the gate trench. A cap layer is formed on thegate. The hard mask layer is then removed. An ion well is formed withinthe epitaxial layer. A source doping region is formed within the ionwell. A spacer is then formed on sidewall of the cap layer and the gate.A self-aligned etching process is then performed to etch the epitaxiallayer using the cap layer and the spacer as an etching hard mask,thereby forming a contact hole.

According to another embodiment, a semiconductor substrate is provided.An epitaxial layer is grown or deposited on the semiconductor substrate.A nitride doping region is then formed at a surface of the epitaxiallayer. A hard mask layer is formed on the epitaxial layer. The hard masklayer comprises at least an opening. Through the opening, agate trenchis etched into the epitaxial layer. Agate oxide layer is then formed inthe gate trench. Agate is formed within the gate trench. The hard masklayer is removed such that the gate protrudes from the surface of theepitaxial layer. An ion well is formed within the epitaxial layer. Asource doping region is formed within the ion well. An upper portion ofthe gate that protrudes from the surface of the epitaxial layer isselectively oxidized to thereby form an oxide capping layer. Using theoxide capping layer as an etching hard mask, the epitaxial layer isself-aligned etched to thereby form a contact hole.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-8 are schematic, cross-sectional diagrams illustrating a methodfor fabricating a trench type power transistor device in accordance withone embodiment of the invention.

FIG. 9 to FIG. 11 depict another embodiment of this invention.

FIGS. 12-18 are schematic, cross-sectional diagrams illustrating amethod for fabricating a trench type power transistor device inaccordance with another embodiment of the invention.

FIGS. 19-21 depict various layouts of the aforesaid contact hole and theaforesaid gate trench.

DETAILED DESCRIPTION

FIGS. 1-8 are schematic, cross-sectional diagrams illustrating a methodfor fabricating a trench type power transistor device in accordance withone embodiment of the invention. As shown in FIG. 1, a semiconductorsubstrate 10, such as an N type heavily doped silicon substrate, isprovided. The semiconductor substrate 10 may act as a drain of thesemiconductor transistor device. Subsequently, an epitaxial process isperformed to form an epitaxial layer 11 such as an N type epitaxialsilicon layer on the semiconductor substrate 10. A hard mask layer 12such as a silicon oxide or silicon nitride may be formed on theepitaxial layer 11. A lithographic process and an etching process areperformed to form openings 112 in the hard mask layer 12. Subsequently,a dry etching process is performed to etch the epitaxial layer 11through the openings 112 to a predetermined depth within epitaxial layer11, thereby forming gate trenches 122.

As shown in FIG. 2, a thermal oxidization process is performed to form agate oxide layer 18 on the surface of each of the gate trenches 122. Achemical vapor deposition (CVD) process is carried out to deposit apolysilicon layer (not shown) in a blanket manner. The depositedpolysilicon layer fills the gate trenches 122. Subsequently, an etchingprocess is performed to etch away a portion of the polysilicon layer tothereby separate trench gates 20 a within the gate trenches 122. At thispoint, a recess region 123 is formed on the trench gate 20 a. It is tobe understood that the trench gate 20 a may be composed of polysilicon,metals or metal silicides, but not limited thereto.

As shown in FIG. 3, a CVD process is carried out to deposit a dielectriclayer (not explicitly shown) such as silicon nitride in a blanketmanner. The dielectric layer fills into the recess region 123.Thereafter, an etching back process or a planarization process isperformed to remove the excess dielectric layer outside the recessregion 123 and thereby expose the hard mask layer 12. The remanentdielectric layer in the recess region 123 forms a cap layer 124.Subsequently, the exposed hard mask layer 12 is removed using methodsknown in the art. At this point, the trench gate 20 a slightly protrudesfrom the surface of the epitaxial layer 11 and a sidewall 201 isrevealed. An oxidization process may be performed to form a siliconoxide layer 118 on the sidewall 201.

As shown in FIG. 4, an ion implantation process is performed to form anion well 210 such as a P well within the epitaxial layer 11. A thermaltreatment may be performed to thermally drive in and diffuse theimplanted dopants. A lithographic process maybe carried out prior to theaforesaid ion implantation process in order to define the well region tobe implanted.

As shown in FIG. 5, another ion implantation process is performed toform source doping region 22 such as N type source doping region withinthe ion well 210. A thermal treatment may be performed to thermallydrive in and diffuse the implanted dopants. Likewise, a lithographicprocess may be carried out prior to the aforesaid ion implantationprocess in order to define the source region to be implanted.

As shown in FIG. 6, a CVD process is carried out to deposit a spacermaterial layer (not explicitly shown) such as a silicon nitride layer ina blanket manner. The spacer material layer is then etched back to forma spacer 130 on each sidewall 201 of the trench gate 20 a and the caplayer 124.

As shown in FIG. 7, a CVD process is performed to deposit a dielectriclayer 140 in a blanket manner. The dielectric layer 140 covers the caplayers 124 and the spacers 130, and fills the space between the spacers130. A lithographic process is then performed to form a resist pattern155 on the dielectric layer 140. The resist pattern 155 comprises anopening 155 a that defines the position of a contact hole to be formed.Subsequently, using the resist pattern 155 as an etching hard mask, thedielectric layer 140 is selectively etched through the opening 155 a tothereby reveal the spacers 130. The epitaxial layer 11 is thenselectively etched to a predetermined depth, thereby forming aself-aligned contact hole 230. The resist pattern 155 is then removed. Acontact hole ion implantation process is performed to form a contactdoping region 250 such as a P+ doping region at the bottom of thecontact hole 230. Thereafter, a rapid thermal anneal maybe carried out.Since the high selectivity between the spacer and the epitaxial layer11, the etching of the contact hole is performed in a self-alignedmanner and the profile of the contact hole is defined by the surface ofthe spacers 130.

FIGS. 19-21 depict various layouts of the aforesaid contact hole 230 andthe aforesaid gate trench 122. For example, FIG. 19 depicts straightline shaped or stripe shaped gate trench 122 and contact hole 230. FIG.20 depicts mesh like gate trench 122 and isolated contact holesurrounded by the gate trench 122. FIG. 21 depicts grid shaped contacthole 230 and isolated gate trench 122 separated by the grid shapedcontact hole 230. Of course, the depicted layouts or patterns areexemplary. It is to be understood that the present invention may beapplicable to other layout patterns.

As shown in FIG. 8, a barrier layer and a meal layer 34 may be depositedto fill the contact hole 230.

FIG. 9 to FIG. 11 depict another embodiment of this invention. As shownin FIG. 9 to FIG. 11, after forming the spacer 130, the dielectric layer140 in FIG. 7 may be omitted and the subsequent resist pattern 155 maybe skipped. Instead, using the cap layer 124 and the spacer 130 as anetching hard mask, the epitaxial layer 11 is etched to a predetermineddepth, thereby forming a self-aligned contact hole 230. Thereafter,contact hole ion implantation process is performed to form contactdoping region 250 at the bottom of the contact hole 230. The barrierlayer and the metal layer 34 are then deposited to fill the contact hole230.

FIGS. 12-18 are schematic, cross-sectional diagrams illustrating amethod for fabricating a trench type power transistor device inaccordance with another embodiment of the invention. As shown in FIG.12, likewise, a semiconductor substrate 10, such as an N type heavilydoped silicon substrate, is provided. The semiconductor substrate 10 mayact as a drain of the semiconductor transistor device. Subsequently, anepitaxial process is performed to form an epitaxial layer 11 such as anN type epitaxial silicon layer on the semiconductor substrate 10. Anitride doping region 101 is then formed at the surface of the epitaxiallayer 11. A hard mask layer 12 such as a silicon oxide or siliconnitride may be formed on the epitaxial layer 11. A lithographic processand an etching process are performed to form openings 112 in the hardmask layer 12. Subsequently, a dry etching process is performed to etchthe epitaxial layer 11 through the openings 112 to a predetermined depthwithin epitaxial layer 11, thereby forming gate trenches 122.

As shown in FIG. 13, a thermal oxidization process is performed to forma gate oxide layer 18 on the surface of each of the gate trenches 122. ACVD process is carried out to deposit a polysilicon layer (not shown) ina blanket manner. The deposited polysilicon layer fills the gatetrenches 122. Subsequently, an etching process is performed to etch awaya portion of the polysilicon layer to thereby separate trench gates 20 awithin the gate trenches 122. At this point, a recess region 123 isformed on the trench gate 20 a.

As shown in FIG. 14, the hard mask layer 12 is selectively removed. Toremove the hard mask layer 12, a photoresist may be coated and filledinto the recess region 123. The photoresist may be etched back. Afterthe hard mask layer 12 is revealed, the hard mask layer 12 is removedand the photoresist is then removed. At this point, the trench gate 20 aslightly protrudes from the surface of the epitaxial layer 11. Anoxidization process is then performed to form a silicon oxide layer 118on the exposed surface of the trench gate 20 a.

As shown in FIG. 15, an ion implantation process is carried out to forman ion well 210 such as a P well in the epitaxial layer 11. A thermalprocess is then performed to drive in or diffuse the implanted dopants.A lithographic process may be carried out prior to the aforesaid ionimplantation process in order to define the well region to be implanted.

As shown in FIG. 16, another ion implantation process is performed toform source doping region 22 such as N type source doping region withinthe ion well 210. A thermal treatment may be performed to thermallydrive in and diffuse the implanted dopants. Likewise, a lithographicprocess may be carried out prior to the aforesaid ion implantationprocess in order to define the source region to be implanted.

As shown in FIG. 17, an oxidization process is then performed toselectively oxidize the upper portion of the trench gate 20 a thatprotrudes from the surface of the epitaxial layer 11, thereby forming anoxide capping layer 150 that laterally extends to cover a portion of theepitaxial layer 11. Due to the nitride doping region 101, the surface ofthe epitaxial layer 11 is substantially not oxidized during theaforesaid oxidization process.

As shown in FIG. 18, subsequently, using the oxide capping layer 150 asan etching hard mask, the epitaxial layer 11 is selectively etched to apredetermined depth, thereby forming a self-aligned contact hole 230.Thereafter, similar to the steps depicted in FIGS. 10-11, contact holeion implantation process may be performed to form contact doping region250 at the bottom of the contact hole 230. The barrier layer and themetal layer 34 is then deposited to fill the contact hole 230.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A method for fabricating a trench type transistordevice, comprising: providing a semiconductor substrate; forming anepitaxial layer on the semiconductor substrate; forming a nitride dopingregion at a surface of the epitaxial layer; forming a hard mask layer onthe epitaxial layer, the hard mask layer comprising at least an opening;through the opening, etching a gate trench into the epitaxial layer;forming a gate oxide layer in the gate trench; forming a gate within thegate trench; removing the hard mask layer such that the gate protrudesfrom the surface of the epitaxial layer; forming an ion well within theepitaxial layer; forming a source doping region within the ion well;selectively oxidizing an upper portion of the gate that protrudes fromthe surface of the epitaxial layer to thereby form an oxide cappinglayer; and using the oxide capping layer as an etching hard mask,self-aligned etching the epitaxial layer to thereby form a contact hole.2. The method for fabricating a trench type transistor device accordingto claim 1 wherein the semiconductor substrate is an N type heavilydoped silicon substrate and acts as a drain of the trench typetransistor device.
 3. The method for fabricating a trench typetransistor device according to claim 2 wherein the epitaxial layer is anN type epitaxial silicon layer.
 4. The method for fabricating a trenchtype transistor device according to claim 1 wherein the hard maskcomprises silicon oxide or silicon nitride.
 5. The method forfabricating a trench type transistor device according to claim 3 whereinthe ion well is a P well.
 6. The method for fabricating a trench typetransistor device according to claim 5 wherein the source doping regionis an N type source doping region.